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| 37 R XA Spartan-3E Automotive FPGA Family Data Sheet 0 DS635 (v2.0) September 9, 2009 Product Specification Summary The Xilinx(R) Automotive (XA) Spartan(R)-3E family of FPGAs is specifically designed to meet the needs of high-volume, cost-sensitive automotive electronics applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates, as shown in Table 1. * - Enhanced Double Data Rate (DDR) support - DDR SDRAM support up to 266 Mb/s Abundant, flexible logic resources - Densities up to 33,192 logic cells, including optional shift register or distributed RAM support - Efficient wide multiplexers, wide logic - Fast look-ahead carry logic - Enhanced 18 x 18 multipliers with optional pipeline - IEEE 1149.1/1532 JTAG programming/debug port Hierarchical SelectRAMTM memory architecture - Up to 648 Kbits of fast block RAM - Up to 231 Kbits of efficient distributed RAM Up to eight Digital Clock Managers (DCMs) - Clock skew elimination (delay locked loop) - Frequency synthesis, multiplication, division - High-resolution phase shifting - Wide frequency range (5 MHz to over 300 MHz) Eight global clocks plus eight additional clocks per each half of device, plus abundant low-skew routing Configuration interface to industry-standard PROMs - Low-cost, space-saving SPI serial Flash PROM - x8 or x8/x16 parallel NOR Flash PROM Complete Xilinx ISE(R) and WebPACKTM software support MicroBlazeTM and PicoBlazeTM embedded processor cores Fully compliant 32-/64-bit 33 MHz PCITM technology support Low-cost QFP and BGA packaging options - Common footprints support easy density migration Introduction XA devices are available in both extended-temperature Q-Grade (-40C to +125C TJ) and I-Grade (-40C to +100C TJ) and are qualified to the industry recognized AEC-Q100 standard. The XA Spartan-3E family builds on the success of the earlier XA Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. These XA Spartan-3E FPGA enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. Because of their exceptionally low cost, XA Spartan-3E FPGAs are ideally suited to a wide range of automotive applications, including infotainment, driver information, and driver assistance modules. The XA Spartan-3E family is a superior alternative to mask programmed ASICs and ASSPs. FPGAs avoid the high initial mask set costs and lengthy development cycles, while also permitting design upgrades in the field with no hardware replacement necessary because of its inherent programmability, an impossibility with conventional ASICs and ASSPs with their inflexible hardware architecture. * * * * * * * * Features * * * Very low-cost, high-performance logic solution for high-volume automotive applications Proven advanced 90-nanometer process technology Multi-voltage, multi-standard SelectIOTM interface pins - Up to 376 I/O pins or 156 differential signal pairs - LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards - 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling - 622+ Mb/s data transfer rate per I/O - True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O Refer to Spartan-3E FPGA Family: Complete Data Sheet (DS312) for a full product description, AC and DC specifications, and package pinout descriptions. Any values shown specifically in this XA Spartan-3E Automotive FPGA Family data sheet override those shown in DS312. For information regarding reliability qualification, refer to RPT081 (Xilinx Spartan-3E Family Automotive Qualification Report) and RPT012 (Spartan-3/3E UMC-12A 90 nm Qualification Report). (c) 2007-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 1 R Key Feature Differences from Commercial XC Devices * AEC-Q100 device qualification and full production part approval process (PPAP) documentation support available in both extended temperature I- and Q-Grades Guaranteed to meet full electrical specification over the TJ = -40C to +125C temperature range (Q-Grade) XA Spartan-3E devices are available in the -4 speed grade only. PCI-66 is not supported in the XA Spartan-3E FPGA product line. The readback feature is not supported in the XA * * * * * * Spartan-3E FPGA product line. XA Spartan-3E devices are available in Step 1 only. JTAG configuration frequency reduced from 30 MHz to 25 MHz. Platform Flash is not supported within the XA family. XA Spartan-3E devices are available in Pb-free packaging only. MultiBoot is not supported in XA versions of this product. The XA Spartan-3E device must be power cycled prior to reconfiguration. * * * * Table 1: Summary of XA Spartan-3E FPGA Attributes CLB Array (One CLB = Four Slices) Equivalent Total Total Logic System Rows Columns CLBs Slices Cells Gates 100K 250K 500K 1200K 1600K 2,160 5,508 10,476 19,512 33,192 22 34 46 60 76 16 26 34 46 58 240 612 1,164 2,168 3,688 960 2,448 4,656 8,672 14,752 Block RAM bits(1) 72K 216K 360K 504K 648K Maximum Maximum Differential I/O Pairs User I/O 108 172 190 304 376 40 68 77 124 156 Device XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E Distributed RAM bits(1) 15K 38K 73K 136K 231K Dedicated Multipliers DCMs 4 12 20 28 36 2 4 4 8 8 Notes: 1. By convention, one Kb is equivalent to 1,024 bits. Architectural Overview The XA Spartan-3E family architecture consists of five fundamental programmable functional elements: * Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data. Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including four high-performance differential standards. Double Data-Rate (DDR) registers are included. Block RAM provides data storage in the form of 18-Kbit dual-port blocks. Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product. * Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. * These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. Each device has two columns of block RAM except for the XA3S100E, which has one column. Each RAM column consists of several 18-Kbit RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are positioned in the center with two at the top and two at the bottom of the device. The XA3S100E has only one DCM at the top and bottom, while the XA3S1200E and XA3S1600E add two DCMs in the middle of the left and right sides. The XA Spartan-3E family features a rich network of traces that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing. * * DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 2 R Notes: 1. The XA3S1200E and XA3S1600E have two additional DCMs on both the left and right sides as indicated by the dashed lines. The XA3S100E has only one DCM at the top and one at the bottom. Figure 1: XA Spartan-3E Family Architecture Configuration XA Spartan-3E FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA's configuration data is stored externally in a PROM or some other non-volatile medium, either on or off the board. After applying power, the configuration data is written to the FPGA using any of five different modes: * * * * * Serial Peripheral Interface (SPI) from an industry-standard SPI serial Flash Byte Peripheral Interface (BPI) Up or Down from an industry-standard x8 or x8/x16 parallel NOR Flash Slave Serial, typically downloaded from a processor Slave Parallel, typically downloaded from a processor Boundary Scan (JTAG), typically downloaded from a processor or system tester. I/O Capabilities The XA Spartan-3E FPGA SelectIO interface supports many popular single-ended and differential standards. Table 2 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. XA Spartan-3E FPGAs support the following single-ended standards: * * * * * 3.3V low-voltage TTL (LVTTL) Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V 3V PCI at 33 MHz HSTL I and III at 1.8V, commonly used in memory applications SSTL I at 1.8V and 2.5V, commonly used for memory applications DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 3 R XA Spartan-3E FPGAs support the following differential standards: * * * * LVDS Bus LVDS mini-LVDS RSDS * * * Differential HSTL (1.8V, Types I and III) Differential SSTL (2.5V and 1.8V, Type I) 2.5V LVPECL inputs Table 2: Available User I/Os and Differential (Diff) I/O Pairs Package Size (mm) Device XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E Notes: 1. 2. All XA Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4: Pinout Descriptions of DS312. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of input-only pins. VQG100 16 x 16 User 66 (7) 66 (7) Diff 30 (2) 30 (2) - CPG132 8x8 User 83 (11) 92 (7) 92 (7) Diff 35 (2) 41 (2) 41 (2) - TQG144 22 x 22 User 108 (28) 108 (28) Diff 40 (4) 40 (4) - PQG208 28 x 28 User 158 (32) 158 (32) Diff 65 (5) 65 (5) - FTG256 17 x 17 User 172 (40) 190 (41) 190 (40) Diff 68 (8) 77 (8) 77 (8) - FGG400 21 x 21 User 304 (72) 304 (72) Diff 124 (20) 124 (20) FGG484 23 x 23 User 376 (82) Diff 156 (21) DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 4 R Package Marking Figure 2 provides a top marking example for XA Spartan-3E FPGAs in the quad-flat packages. Figure 3 shows the top marking for XA Spartan-3E FPGAs in BGA packages except the 132-ball chip-scale package (CPG132). The markings for the BGA packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball A1 indicator. Figure 4 shows the top marking for XA Spartan-3E FPGAs in the CPG132 package. Note: No marking is shown for stepping. Mask Revision Code Fabrication Code R SPARTAN Device Type Package Speed Grade Temperature Range R Process Technology Date Code Lot Code XA3S250E TM PQG208AGQ0525 D1234567A 4I Pin P1 DS635-1_02_082807 Figure 2: XA Spartan-3E FPGA QFP Package Marking Example Mask Revision Code BGA Ball A1 Device Type Package R SPARTAN R Fabrication Code Process Code XA3S250ETM FTG256AGQ0525 FTG256AGQ0525 D1234567A D1234567A 4I Date Code Lot Code Speed Grade Temperature Range DS635_03_082807 Figure 3: XA Spartan-3E FPGA BGA Package Marking Example Ball A1 Lot Code 3S250E F1234567-0525 PHILIPPINES Device Type Date Code Temperature Range Package C6 = CPG132 C6AGQ 4I Speed Grade Process Code Fabrication Code DS635_04_082807 Mask Revision Code Figure 4: XA Spartan-3E FPGA CPG132 Package Marking Example DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 5 R Ordering Information XA Spartan-3E FPGAs are available in Pb-free packaging options for all device/package combinations. All devices are in Pb-free packages only, with a "G" character to the ordering code. All devices are available in either I-Grade or Q-Grade temperature ranges. Only the -4 speed grade is available for the XA Spartan-3E family. See Table 2 for valid device/package combinations. Pb-Free Packaging Example: Device Type Speed Grade Package Type XA3S250E -4 FT G 256 I Temperature Range: I = I-Grade (TJ = -40oC to 100oC) Q = Q-Grade (TJ = -40oC to 125oC) Number of Pins Pb-free DS635_06_121608 Device XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E Speed Grade -4 Only VQG100 CPG132 TQG144 PQG208 FTG256 FGG400 FGG484 Package Type / Number of Pins 100-pin Very Thin Quad Flat Pack (VQFP) 132-ball Chip-Scale Package (CSP) 144-pin Thin Quad Flat Pack (TQFP) 208-pin Plastic Quad Flat Pack (PQFP) 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) 400-ball Fine-Pitch Ball Grid Array (FBGA) 484-ball Fine-Pitch Ball Grid Array (FBGA) Temperature Range ( TJ ) I I-Grade (-40C to 100C) Q Q-Grade (-40C to 125C) DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 6 R Power Supply Specifications Table 3: Supply Voltage Thresholds for Power-On Reset Symbol VCCINTT VCCAUXT VCCO2T Notes: 1. 2. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA's configuration source (SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with no dips at any point. Description Threshold for the VCCINT supply Threshold for the VCCAUX supply Threshold for the VCCO Bank 2 supply Min 0.4 0.8 0.4 Max 1.0 2.0 1.0 Units V V V Table 4: Supply Voltage Ramp Rate Symbol VCCINTR VCCAUXR VCCO2R Notes: 1. 2. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA's configuration source (SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with no dips at any point. Description Ramp rate from GND to valid VCCINT supply level Ramp rate from GND to valid VCCAUX supply level Ramp rate from GND to valid VCCO Bank 2 supply level Min 0.2 0.2 0.2 Max 50 50 50 Units ms ms ms Table 5: Supply Voltage Levels Necessary for Preserving RAM Contents Symbol VDRINT VDRAUX Notes: 1. RAM contents include configuration data. Description VCCINT level required to retain RAM data VCCAUX level required to retain RAM data Min 1.0 2.0 Units V V DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 7 R DC Specifications Table 6: General Recommended Operating Conditions Symbol TJ VCCINT VCCO (1) Description Junction temperature Internal supply voltage Output driver supply voltage Auxiliary supply voltage Voltage variance on VCCAUX when using a DCM Input voltage extremes to avoid turning on I/O protection diodes Input signal transition time(7) I/O, Input-only, and Dual-Purpose pins(3) Dedicated pins(4) I-Grade Q-Grade Min -40 -40 1.140 1.100 2.375 -0.5 -0.5 - Nominal 25 25 1.200 2.500 - - - Max 100 125 1.260 3.465 2.625 10 VCCO + 0.5 VCCAUX + 0.5 500 Units C C V V V mV/ms V V ns VCCAUX VCCAUX (2) VIN(3,4,5,6) TIN Notes: 1. 2. 3. 4. 5. 6. 7. This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 9 lists the recommended VCCO range specific to each of the single-ended I/O standards, and Table 11 lists that specific to the differential standards. Only during DCM operation is it recommended that the rate of change of VCCAUX not exceed 10 mV/ms. Each of the User I/O and Dual-Purpose pins is associated with one of the four banks' VCCO rails. Meeting the VIN limit ensures that the internal diode junctions that exist between these pins and their associated VCCO and GND rails do not turn on. See Absolute Maximum Ratings in DS312). All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V). Meeting the VIN max limit ensures that the internal diode junctions that exist between each of these pins and the VCCAUX and GND rails do not turn on. Input voltages outside the recommended range is permissible provided that the IIK input clamp diode rating is met and no more than 100 pins exceed the range simultaneously. See Absolute Maximum Ratings in DS312). See XAPP459, "Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins." Measured between 10% and 90% VCCO. Follow Signal Integrity recommendations. General DC Characteristics for I/O Pins Table 7: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol IL Description Leakage current at User I/O, Input-only, Dual-Purpose, and Dedicated pins Current through pull-up resistor at User I/O, Dual-Purpose, Input-only, and Dedicated pins Test Conditions Driver is in a high-impedance state, VIN = 0V or VCCO max, sample-tested VIN = 0V, VCCO = 3.3V VIN = 0V, VCCO = 2.5V VIN = 0V, VCCO = 1.8V VIN = 0V, VCCO = 1.5V VIN = 0V, VCCO = 1.2V RPU(2) Equivalent pull-up resistor value at User I/O, Dual-Purpose, Input-only, and Dedicated pins (based on IRPU per Note 2) VIN = 0V, VCCO = 3.0V to 3.465V VIN = 0V, VCCO = 2.3V to 2.7V VIN = 0V, VCCO = 1.7V to 1.9V VIN = 0V, VCCO =1.4V to 1.6V VIN = 0V, VCCO = 1.14V to 1.26V Min -10 Typ - Max +10 Units A IRPU(2) -0.36 -0.22 -0.10 -0.06 -0.04 2.4 2.7 4.3 5.0 5.5 - - - - - - - - - - -1.24 -0.80 -0.42 -0.27 -0.22 10.8 11.8 20.2 25.9 32.0 mA mA mA mA mA k k k k k DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 8 R Table 7: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (Continued) Symbol IRPD(2) Description Current through pull-down resistor at User I/O, Dual-Purpose, Input-only, and Dedicated pins Equivalent pull-down resistor value at User I/O, Dual-Purpose, Input-only, and Dedicated pins (based on IRPD per Note 2) Test Conditions VIN = VCCO Min 0.10 Typ - Max 0.75 Units mA RPD(2) VIN = VCCO = 3.0V to 3.45V VIN = VCCO = 2.3V to 2.7V VIN = VCCO = 1.7V to 1.9V VIN = VCCO = 1.4V to 1.6V VIN = VCCO = 1.14V to 1.26V 4.0 3.0 2.3 1.8 1.5 -10 - - - - - - - - - 120 34.5 27.0 19.0 16.0 12.6 +10 10 - k k k k k A pF IREF CIN RDT VREF current per pin Input capacitance Resistance of optional differential termination circuit within a differential I/O pair. Not available on Input-only pairs. All VCCO levels VOCM Min VICM VOCM Max VOD Min VID VOD Max VCCO = 2.5V Notes: 1. 2. The numbers in this table are based on the conditions set forth in Table 6. This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD. Table 8: Quiescent Supply Current Characteristics Symbol ICCINTQ Description Quiescent VCCINT supply current Device XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E ICCOQ Quiescent VCCO supply current XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E I-Grade Maximum 36 104 145 324 457 1.5 1.5 1.5 2.5 2.5 Q-Grade Maximum 58 158 300 500 750 2.0 3.0 3.0 4.0 4.0 Units mA mA mA mA mA mA mA mA mA mA DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 9 R Table 8: Quiescent Supply Current Characteristics (Continued) Symbol ICCAUXQ Description Quiescent VCCAUX supply current Device XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E Notes: 1. 2. The numbers in this table are based on the conditions set forth in Table 6. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are characterized using typical devices at room temperature (TJ of 25C at VCCINT = 1.2 V, VCCO = 3.3V, and VCCAUX = 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with VCCINT = 1.26V, VCCO = 3.465V, and VCCAUX = 2.625V. The FPGA is programmed with a "blank" configuration data file (i.e., a design with no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional elements), measured quiescent current levels may be different than the values in the table. For more accurate estimates for a specific design, use the Xilinx XPower tools. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3E XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully. I-Grade Maximum 13 26 34 59 86 Q-Grade Maximum 22 43 63 100 150 Units mA mA mA mA mA 3. 4. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 10 R Single-Ended I/O Standards Table 9: Recommended Operating Conditions for User I/Os Using Single-Ended Standards IOSTANDARD Attribute LVTTL LVCMOS33(4) LVCMOS25(4,5) LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 HSTL_I_18 HSTL_III_18 SSTL18_I SSTL2_I Notes: 1. Descriptions of the symbols used in this table are as follows: VCCO - the supply voltage for output drivers VREF - the reference voltage for setting the input switching threshold VIL - the input voltage that indicates a Low logic level VIH - the input voltage that indicates a High logic level The VCCO rails supply only output drivers, not input circuits. For device operation, the maximum signal voltage (VIH max) may be as high as VIN max. See Table 72 in DS312. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw power from the VCCAUX rail (2.5V). The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as well as throughout configuration. For information on PCI IP solutions, see www.xilinx.com/pci. VCCO for Drivers(2) Min (V) 3.0 3.0 2.3 1.65 1.4 1.1 3.0 1.7 1.7 1.7 2.3 Nom (V) 3.3 3.3 2.5 1.8 1.5 1.2 3.3 1.8 1.8 1.8 2.5 Max (V) 3.465 3.465 2.7 1.95 1.6 1.3 3.465 1.9 1.9 1.9 2.7 0.8 0.833 1.15 Min (V) VREF Nom (V) Max (V) VIL Max (V) 0.8 0.8 0.7 VIH Min (V) 2.0 2.0 1.7 0.8 0.8 0.7 0.5 * VCCO VREF + 0.1 VREF + 0.1 VREF + 0.125 VREF + 0.125 VREF is not used for these I/O standards 0.4 0.4 0.4 0.3 * VCCO 0.9 1.1 0.900 1.25 1.1 0.969 1.35 VREF - 0.1 VREF - 0.1 VREF - 0.125 VREF - 0.125 2. 3. 4. 5. 6. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 11 R Table 10: DC Characteristics of User I/Os Using Single-Ended Standards Test Conditions IOSTANDARD Attribute LVTTL(3) 2 4 6 8 12 16 LVCMOS33(3) 2 4 6 8 12 16 LVCMOS25(3) 2 4 6 8 12 LVCMOS18(3) 2 4 6 8 LVCMOS15(3) 2 4 6 IOL (mA) Table 10: DC Characteristics of User I/Os Using Single-Ended Standards (Continued) Test Conditions IOSTANDARD Attribute LVCMOS12(3) PCI33_3(4) HSTL_I_18 HSTL_III_18 SSTL18_I SSTL2_I 2 IOL (mA) Logic Level Characteristics VOL Max (V) 0.4 VOH Min (V) 2.4 Logic Level Characteristics VOL Max (V) 0.4 10% VCCO 0.4 0.4 VTT - 0.475 IOH (mA) IOH (mA) VOH Min (V) VCCO - 0.4 90% VCCO VCCO - 0.4 VCCO - 0.4 VTT + 0.475 2 4 6 8 12 16 2 4 6 8 12 16 2 4 6 8 12 2 4 6 8 2 4 6 -2 -4 -6 -8 -12 -16 -2 -4 -6 -8 -12 -16 -2 -4 -6 -8 -12 -2 -4 -6 -8 -2 -4 -6 2 1.5 8 24 6.7 8.1 -2 -0.5 -8 -8 -6.7 -8.1 VTT - 0.61 VTT + 0.61 0.4 VCCO - 0.4 Notes: 1. 2. The numbers in this table are based on the conditions set forth in Table 6 and Table 9. Descriptions of the symbols used in this table are as follows: IOL - the output current condition under which VOL is tested IOH - the output current condition under which VOH is tested VOL - the output voltage that indicates a Low logic level VOH - the output voltage that indicates a High logic level VCCO - the supply voltage for output drivers VTT - the voltage applied to a resistor termination 0.4 VCCO - 0.4 3. 4. For the LVCMOS and LVTTL standards: the same VOL and VOH limits apply for both the Fast and Slow slew attributes. Tested according to the relevant PCI specifications. For information on PCI IP solutions, see www.xilinx.com/pci. 0.4 VCCO - 0.4 0.4 VCCO - 0.4 DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 12 R Differential I/O Standards Table 11: Recommended Operating Conditions for User I/Os Using Differential Signal Standards VCCO for Drivers(1) VID Min (mV) 100 100 200 100 2.625 1.9 1.9 1.9 2.7 100 100 100 100 100 Nom (mV) 350 350 800 200 Max (mV) 600 600 600 1000 Min (V) 0.30 0.30 0.30 0.5 0.3 0.8 0.8 0.7 1.0 VICM Nom (V) 1.25 1.25 1.2 1.20 Max (V) 2.20 2.20 2.2 2.0 1.4 1.1 1.1 1.1 1.5 IOSTANDARD Attribute LVDS_25 BLVDS_25 MINI_LVDS_25 LVPECL_25(2) RSDS_25 DIFF_HSTL_I_18 DIFF_HSTL_III_18 DIFF_SSTL18_I DIFF_SSTL2_I Notes: 1. 2. Min (V) 2.375 2.375 2.375 Nom (V) 2.50 2.50 2.50 Inputs Only Max (V) 2.625 2.625 2.625 2.375 1.7 1.7 1.7 2.3 2.50 1.8 1.8 1.8 2.5 The VCCO rails supply only differential output drivers, not input circuits. VREF inputs are not used for any of the differential I/O standards. Table 12: DC Characteristics of User I/Os Using Differential Signal Standards VOD IOSTANDARD Attribute LVDS_25 BLVDS_25 MINI_LVDS_25 RSDS_25 DIFF_HSTL_I_18 DIFF_HSTL_III_18 DIFF_SSTL18_I DIFF_SSTL2_I Notes: 1. 2. 3. The numbers in this table are based on the conditions set forth in Table 6, and Table 11. Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100 across the N and P pins of the differential signal pair. The exception is for BLVDS, shown in Figure 5 below. At any given time, no more than two of the following differential output standards may be assigned to an I/O bank: LVDS_25, RSDS_25, MINI_LVDS_25 VOD Max (mV) 450 450 600 400 - - - - Min (mV) - - - - - - - - Max (mV) - - 50 - - - - - Min (V) 1.125 - 1.0 1.1 - - - - VOCM Typ (V) - 1.20 - - - - - - Max (V) 1.375 - 1.4 1.4 - - - - VOCM Min (mV) - - - - - - - - Max (mV) - - 50 - - - - - VOH Min (V) - - - - VCCO - 0.4 VCCO - 0.4 VTT + 0.475 VOL Max (V) - - - - 0.4 0.4 VTT - 0.475 Min (mV) 250 250 300 100 - - - - Typ (mV) 350 350 - - - - - - VTT + 0.61 VTT - 0.61 DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 13 R 1/4th of Bourns Part Number CAT16-LV4F12 1/4th of Bourns Part Number CAT16-PT4F4 VCCO = 2.5V 165 140 165 Z0 = 50 100 VCCO = 2.5V Z0 = 50 DS635_05_082807 Figure 5: External Termination Resistors for BLVDS Transmitter and BLVDS Receiver Switching Characteristics I/O Timing Table 13: Pin-to-Pin Clock-to-Output Times for the IOB Output Path -4 Speed Grade Symbol Clock-to-Output Times TICKOFDCM When reading from the Output Flip-Flop (OFF), the time from the active transition on the Global Clock pin to data appearing at the Output pin. The DCM is used. LVCMOS25(2), 12mA output drive, Fast slew rate, with DCM(3) XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E Description Conditions Device Max Units 2.79 3.45 3.46 3.46 3.45 5.92 5.43 5.51 5.94 6.05 ns ns ns ns ns ns ns ns ns ns TICKOF When reading from OFF, the time from the active transition on the Global Clock pin to data appearing at the Output pin. The DCM is not used. LVCMOS25(2), 12mA output drive, Fast slew rate, without DCM XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E Notes: 1. 2. 3. 4. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6 and Table 9. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate Input adjustment from Table 17. If the latter is true, add the appropriate Output adjustment from Table 18. DCM output jitter is included in all measurements. For minimums, use the values reported by the Xilinx timing analyzer. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 14 R Table 14: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous) IFD_ DELAY_ VALUE= 0 -4 Speed Grade Device XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E LVCMOS25(2), IFD_DELAY_VALUE = default software setting 2 3 2 5 4 Hold Times TPHDCM When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is used. No Input Delay is programmed. When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is not used. The Input Delay is programmed. LVCMOS25(3), IFD_DELAY_VALUE = 0, with DCM(4) 0 XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E LVCMOS25(3), IFD_DELAY_VALUE = default software setting 2 3 2 5 4 XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E -0.52 0.14 0.14 0.15 0.14 -0.24 -0.32 -0.49 -0.63 -0.39 ns ns ns ns ns ns ns ns ns ns XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E Min 2.98 2.59 2.59 2.58 2.59 3.58 3.91 4.02 5.52 4.46 Units ns ns ns ns ns ns ns ns ns ns Symbol Setup Times TPSDCM Description When writing to the Input Flip-Flop (IFF), the time from the setup of data at the Input pin to the active transition at a Global Clock pin. The DCM is used. No Input Delay is programmed. When writing to IFF, the time from the setup of data at the Input pin to an active transition at the Global Clock pin. The DCM is not used. The Input Delay is programmed. Conditions LVCMOS25(2), IFD_DELAY_VALUE = 0, with DCM(4) TPSFD TPHFD Notes: 1. 2. 3. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6 and Table 9. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 17. If this is true of the data Input, add the appropriate Input adjustment from the same table. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 17. If this is true of the data Input, subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock's active edge. DCM output jitter is included in all measurements. 4. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 15 R Table 15: Setup and Hold Times for the IOB Input Path IFD_ DELAY_ VALUE -4 Speed Grade Device Min Units Symbol Setup Times TIOPICK Description Conditions LVCMOS25(2), IFD_DELAY_VALUE = 0 Time from the setup of data at the Input pin to the active transition at the ICLK input of the Input Flip-Flop (IFF). No Input Delay is programmed. Time from the setup of data at the Input pin to the active transition at the IFF's ICLK input. The Input Delay is programmed. 0 All 2.12 ns TIOPICKD LVCMOS25(2), IFD_DELAY_VALUE = default software setting 2 3 2 5 4 XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E 6.49 6.85 7.01 8.67 7.69 ns ns ns ns ns Hold Times TIOICKP Time from the active transition at the IFF's ICLK input to the point where data must be held at the Input pin. No Input Delay is programmed. Time from the active transition at the IFF's ICLK input to the point where data must be held at the Input pin. The Input Delay is programmed. LVCMOS25(2), IFD_DELAY_VALUE = 0 0 All -0.76 ns TIOICKPD LVCMOS25(2), IFD_DELAY_VALUE = default software setting 2 3 2 5 4 XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E -3.93 -3.51 -3.74 -4.30 -4.14 ns ns ns ns ns Set/Reset Pulse Width TRPW_IOB Notes: 1. 2. 3. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6 and Table 9. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the appropriate Input adjustment from Table 17. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract the appropriate Input adjustment from Table 17. When the hold time is negative, it is possible to change the data before the clock's active edge. Minimum pulse width to SR control input on IOB All 1.80 ns DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 16 R Table 16: Propagation Times for the IOB Input Path IFD_ DELAY_ VALUE -4 Speed Grade Device Max Units Symbol Propagation Times TIOPLI Description Conditions The time it takes for data to travel from the Input pin through the IFF latch to the I output with no input delay programmed The time it takes for data to travel from the Input pin through the IFF latch to the I output with the input delay programmed LVCMOS25(2), IFD_DELAY_VALUE = 0 0 All 2.25 ns TIOPLID LVCMOS25(2), IFD_DELAY_VALUE = default software setting 2 3 2 5 4 XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E 5.97 6.33 6.49 8.15 7.16 ns ns ns ns ns Notes: 1. 2. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6 and Table 9. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is true, add the appropriate Input adjustment from Table 17. Table 17: Input Timing Adjustments by IOSTANDARD Convert Input Time from LVCMOS25 to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 HSTL_I_18 HSTL_III_18 SSTL18_I SSTL2_I 0.43 0.43 0 0.98 0.63 0.27 0.42 0.12 0.17 0.30 0.15 ns ns ns ns ns ns ns ns ns ns ns Add the Adjustment Below -4 Speed Grade Units Table 17: Input Timing Adjustments by IOSTANDARD Convert Input Time from LVCMOS25 to the Following Signal Standard (IOSTANDARD) Differential Standards LVDS_25 BLVDS_25 MINI_LVDS_25 LVPECL_25 RSDS_25 DIFF_HSTL_I_18 DIFF_HSTL_III_18 DIFF_SSTL18_I DIFF_SSTL2_I Notes: 1. 2. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6, Table 9, and Table 11. These adjustments are used to convert input path times originally specified for the LVCMOS25 standard to times that correspond to other signal standards. Add the Adjustment Below -4 Speed Grade Units 0.49 0.39 0.49 0.27 0.49 0.49 0.49 0.30 0.32 ns ns ns ns ns ns ns ns ns DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 17 R Table 18: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL Slow 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Fast 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA LVCMOS33 Slow 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Fast 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA LVCMOS25 Slow 2 mA 4 mA 6 mA 8 mA 12 mA Fast 2 mA 4 mA 6 mA 8 mA 12 mA 5.41 2.41 1.90 0.67 0.70 0.43 5.00 1.96 1.45 0.34 0.30 0.30 5.29 1.89 1.04 0.69 0.42 0.43 4.87 1.52 0.39 0.34 0.30 0.30 4.21 2.26 1.52 1.08 0.68 3.67 1.72 0.46 0.21 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Add the Adjustment Below -4 Speed Grade Units Table 18: Output Timing Adjustments for IOB (Continued) Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS18 Slow 2 mA 4 mA 6 mA 8 mA Fast 2 mA 4 mA 6 mA 8 mA LVCMOS15 Slow 2 mA 4 mA 6 mA Fast 2 mA 4 mA 6 mA LVCMOS12 HSTL_I_18 HSTL_III_18 PCI33_3 SSTL18_I SSTL2_I Differential Standards LVDS_25 BLVDS_25 MINI_LVDS_25 LVPECL_25 RSDS_25 DIFF_HSTL_I_18 DIFF_HSTL_III_18 DIFF_SSTL18_I DIFF_SSTL2_I Notes: 1. 2. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6, Table 9, and Table 11. These adjustments are used to convert output- and three-state-path times originally specified for the LVCMOS25 standard with 12 mA drive and Fast slew rate to times that correspond to other signal standards. Do not adjust times that measure when outputs go into a high-impedance state. Add the Adjustment Below -4 Speed Grade 5.24 3.21 2.49 1.90 4.15 2.13 1.14 0.75 4.68 3.97 3.11 3.38 2.70 1.53 6.63 4.44 0.34 0.55 0.46 0.25 -0.20 -0.55 0.04 -0.56 Input Only -0.48 0.42 0.55 0.40 0.44 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Slow Fast 2 mA 2 mA DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 18 R Table 19: Test Methods for Timing Measurement at I/Os Signal Standard (IOSTANDARD) Single-Ended LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 Rising Falling HSTL_I_18 HSTL_III_18 SSTL18_I SSTL2_I Differential LVDS_25 BLVDS_25 MINI_LVDS_25 LVPECL_25 RSDS_25 DIFF_HSTL_I_18 DIFF_HSTL_III_18 DIFF_SSTL18_I DIFF_SSTL2_I Notes: 1. Descriptions of the relevant symbols are as follows: VREF - The reference voltage for setting the input switching threshold VICM - The common mode input voltage VM - Voltage of measurement point on signal transition VL - Low-level test voltage at Input pin VH - High-level test voltage at Input pin RT - Effective termination resistance, which takes on a value of 1M when no parallel termination is required VT - Termination voltage The load capacitance (CL) at the Output pin is 0 pF for all signal standards. According to the PCI specification. Inputs VREF (V) VL (V) 0 0 0 0 0 0 Note 3 VH (V) 3.3 3.3 2.5 1.8 1.5 1.2 Note 3 RT () 1M 1M 1M 1M 1M 1M 25 25 0.9 1.1 0.9 1.25 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.75 VICM - 0.125 VICM - 0.125 VICM - 0.125 VICM - 0.3 VICM - 0.1 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.75 VICM + 0.125 VICM + 0.125 VICM + 0.125 VICM + 0.3 VICM + 0.1 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 50 50 50 50 Outputs VT (V) 0 0 0 0 0 0 0 3.3 0.9 1.8 0.9 1.25 Inputs and Outputs VM (V) 1.4 1.65 1.25 0.9 0.75 0.6 0.94 2.03 VREF VREF VREF VREF VICM VICM VICM VICM VICM VICM VICM VICM VICM - 50 1M 50 1M 50 50 50 50 50 1.2 0 1.2 0 1.2 0.9 1.8 0.9 1.25 2. 3. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 19 R Configurable Logic Block Timing Table 20: CLB (SLICEM) Timing -4 Speed Grade Symbol Clock-to-Output Times TCKO Setup Times TAS TDICK Hold Times TAH TCKDI Clock Timing TCH TCL FTOG The High pulse width of the CLB's CLK signal The Low pulse width of the CLK signal Toggle frequency (for export control) 0.80 0.80 0 572 ns ns MHz Time from the active transition at the CLK input to the point where data is last held at the F or G input Time from the active transition at the CLK input to the point where data is last held at the BX or BY input 0 0 ns ns Time from the setup of data at the F or G input to the active transition at the CLK input of the CLB Time from the setup of data at the BX or BY input to the active transition at the CLK input of the CLB 0.52 1.81 ns ns When reading from the FFX (FFY) Flip-Flop, the time from the active transition at the CLK input to data appearing at the XQ (YQ) output 0.60 ns Description Min Max Units Propagation Times TILO The time it takes for data to travel from the CLB's F (G) input to the X (Y) output 0.76 ns Set/Reset Pulse Width TRPW_CLB Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6. The minimum allowable pulse width, High or Low, to the CLB's SR input 1.80 - ns DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 20 R Table 21: CLB Distributed RAM Switching Characteristics -4 Symbol Clock-to-Output Times TSHCKO Setup Times TDS TAS TWS Hold Times TDH TAH, TWH Hold time of the BX, BY data inputs after the active transition at the CLK input of the distributed RAM Hold time of the F/G address inputs or the write enable input after the active transition at the CLK input of the distributed RAM 0.15 0 ns ns Setup time of data at the BX or BY input before the active transition at the CLK input of the distributed RAM Setup time of the F/G address inputs before the active transition at the CLK input of the distributed RAM Setup time of the write enable input before the active transition at the CLK input of the distributed RAM 0.46 0.52 0.40 ns ns ns Time from the active edge at the CLK input to data appearing on the distributed RAM output 2.35 ns Description Min Max Units Clock Pulse Width TWPH, TWPL Minimum High or Low pulse width at CLK input 1.01 ns Table 22: CLB Shift Register Switching Characteristics -4 Symbol Clock-to-Output Times TREG Setup Times TSRLDS Hold Times TSRLDH Hold time of the BX or BY data input after the active transition at the CLK input of the shift register 0.16 ns Setup time of data at the BX or BY input before the active transition at the CLK input of the shift register 0.46 ns Time from the active edge at the CLK input to data appearing on the shift register output 4.16 ns Description Min Max Units Clock Pulse Width TWPH, TWPL Minimum High or Low pulse width at CLK input 1.01 ns DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 21 R Clock Buffer/Multiplexer Switching Characteristics Table 23: Clock Distribution Switching Characteristics Maximum Description Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as BUFGCE enable CE-input Frequency of signals distributed on global buffers (all sides) Symbol TGIO TGSI FBUFG -4 Speed Grade 1.46 0.63 311 Units ns ns MHz 18 x 18 Embedded Multiplier Timing Table 24: 18 x 18 Embedded Multiplier Timing -4 Speed Grade Symbol Combinatorial Delay TMULT Combinatorial multiplier propagation delay from the A and B inputs to the P outputs, assuming 18-bit inputs and a 36-bit product (AREG, BREG, and PREG registers unused) 4.88(1) ns Description Min Max Units Clock-to-Output Times TMSCKP_P TMSCKP_A TMSCKP_B Setup Times TMSDCK_P Data setup time at the A or B input before the active transition at the CLK when using only the PREG output register (AREG, BREG registers unused)(2) Data setup time at the A input before the active transition at the CLK when using the AREG input register(3) Data setup time at the B input before the active transition at the CLK when using the BREG input register(3) 3.98 ns Clock-to-output delay from the active transition of the CLK input to valid data appearing on the P outputs when using the PREG register(2) Clock-to-output delay from the active transition of the CLK input to valid data appearing on the P outputs when using either the AREG or BREG register(3) 1.10 ns - 4.97 ns TMSDCK_A TMSDCK_B Hold Times TMSCKD_P 0.23 0.39 - ns ns Data hold time at the A or B input before the active transition at the CLK when using only the PREG output register (AREG, BREG registers unused)(2) Data hold time at the A input before the active transition at the CLK when using the AREG input register(3) Data hold time at the B input before the active transition at the CLK when using the BREG input register(3) -0.97 TMSCKD_A TMSCKD_B 0.04 0.05 DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 22 R Table 24: 18 x 18 Embedded Multiplier Timing (Continued) -4 Speed Grade Symbol Clock Frequency FMULT Notes: 1. 2. 3. Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations. Input registers AREG or BREG are typically used when inferring a two-stage multiplier. Description Min Max Units Internal operating frequency for a two-stage 18x18 multiplier using the AREG and BREG input registers and the PREG output register(1) 0 240 MHz Block RAM Timing Table 25: Block RAM Timing -4 Speed Grade Symbol Clock-to-Output Times TBCKO Setup Times TBACK TBDCK TBECK TBWCK Hold Times TBCKA TBCKD TBCKE TBCKW Hold time on the ADDR inputs after the active transition at the CLK input Hold time on the DIN inputs after the active transition at the CLK input Hold time on the EN input after the active transition at the CLK input Hold time on the WE input after the active transition at the CLK input 0.14 0.13 0 0 ns ns ns ns Setup time for the ADDR inputs before the active transition at the CLK input of the block RAM Setup time for data at the DIN inputs before the active transition at the CLK input of the block RAM Setup time for the EN input before the active transition at the CLK input of the block RAM Setup time for the WE input before the active transition at the CLK input of the block RAM 0.38 0.23 0.77 1.26 ns ns ns ns When reading from block RAM, the delay from the active transition at the CLK input to data appearing at the DOUT output 2.82 ns Description Min Max Units DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 23 R Table 25: Block RAM Timing (Continued) -4 Speed Grade Symbol Clock Timing TBPWH TBPWL High pulse width of the CLK signal Low pulse width of the CLK signal 1.59 1.59 ns ns Description Min Max Units Clock Frequency FBRAM Block RAM clock frequency. RAM read output value written back into RAM, for shift registers and circular buffers. Write-only or read-only performance is faster. 0 230 MHz Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6. Digital Clock Manager Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table 26 and Table 27) apply to any application that only employs the DLL component. When the DFS and/or the PS components are used together with the DLL, then the specifications listed in the DFS and PS tables (Table 28 through Table 31) supersede any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions are presented in Table 26 and Table 27. Period jitter and cycle-cycle jitter are two of many different ways of specifying clock jitter. Both specifications describe statistical variation from a mean value. Period jitter is the worst-case deviation from the ideal clock period over a collection of millions of samples. In a histogram of period jitter, the mean value is the clock period. Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean value is zero. Spread Spectrum DCMs accept typical spread spectrum clocks as long as they meet the input requirements. The DLL will track the frequency changes created by the spread spectrum clock to drive the global clocks to the FPGA logic. See XAPP469, Spread-Spectrum Clocking Reception for Displays for details. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 24 R Delay-Locked Loop Table 26: Recommended Operating Conditions for the DLL -4 Speed Grade Symbol Input Frequency Ranges FCLKIN CLKIN_FREQ_DLL Frequency of the CLKIN clock input 5(2) 240(3) MHz Description Min Max Units Input Pulse Requirements CLKIN_PULSE CLKIN pulse width as a percentage of the CLKIN period FCLKIN < 150 MHz FCLKIN > 150 MHz 40% 45% 60% 55% - Input Clock Jitter Tolerance and Delay Path Variation(4) CLKIN_CYC_JITT_DLL_LF CLKIN_CYC_JITT_DLL_HF CLKIN_PER_JITT_DLL CLKFB_DELAY_VAR_EXT Notes: 1. 2. 3. 4. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 28. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input. CLKIN input jitter beyond these limits might cause the DCM to lose lock. Cycle-to-cycle jitter at the CLKIN input Period jitter at the CLKIN input FCLKIN < 150 MHz FCLKIN > 150 MHz - 300 150 1 1 ps ps ns ns Allowable variation of off-chip feedback delay from the DCM output to the CLKFB input Table 27: Switching Characteristics for the DLL -4 Speed Grade Symbol Output Frequency Ranges CLKOUT_FREQ_CLK0 CLKOUT_FREQ_CLK90 CLKOUT_FREQ_2X CLKOUT_FREQ_DV Output Clock Jitter(2,3,4) Period jitter at the CLK0 output Period jitter at the CLK90 output Period jitter at the CLK180 output Period jitter at the CLK270 output Period jitter at the CLK2X and CLK2X180 outputs 100 150 150 150 [1% of CLKIN period + 150] 150 [1% of CLKIN period + 200] ps ps ps ps ps Frequency for the CLK0 and CLK180 outputs Frequency for the CLK90 and CLK270 outputs Frequency for the CLK2X and CLK2X180 outputs Frequency for the CLKDV output 5 5 10 0.3125 240 200 311 160 MHz MHz MHz MHz Description Min Max Units CLKOUT_PER_JITT_0 CLKOUT_PER_JITT_90 CLKOUT_PER_JITT_180 CLKOUT_PER_JITT_270 CLKOUT_PER_JITT_2X CLKOUT_PER_JITT_DV1 CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when performing integer division Period jitter at the CLKDV output when performing non-integer division - ps ps DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 25 R Table 27: Switching Characteristics for the DLL (Continued) -4 Speed Grade Symbol Duty Cycle(4) Duty cycle variation for the CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV outputs, including the BUFGMUX and clock tree duty-cycle distortion [1% of CLKIN period + 400] ps Description Min Max Units CLKOUT_DUTY_CYCLE_DLL Phase Alignment(4) CLKIN_CLKFB_PHASE CLKOUT_PHASE_DLL Phase offset between the CLKIN and CLKFB inputs Phase offset between DLL outputs CLK0 to CLK2X (not CLK2X180) All others 200 [1% of CLKIN period + 100] [1% of CLKIN period + 200] ps ps - ps Lock Time LOCK_DLL(3) When using the DLL alone: The time from deassertion at the DCM's Reset input to the rising transition at its LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase 5 MHz < FCLKIN < 15 MHz FCLKIN > 15 MHz 5 600 ms s Delay Lines DCM_DELAY_STEP Finest delay resolution 20 40 ps Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 26. 2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input. 3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. 4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. Example: The data sheet specifies a maximum jitter of "[1% of CLKIN period + 150]". Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 150 ps] = 250ps. Digital Frequency Synthesizer Table 28: Recommended Operating Conditions for the DFS -4 Speed Grade Symbol Input Frequency Ranges(2) FCLKIN CLKIN_FREQ_FX Frequency for the CLKIN input Cycle-to-cycle jitter at the CLKIN input, based on CLKFX output frequency Period jitter at the CLKIN input FCLKFX < 150 MHz FCLKFX > 150 MHz 0.200 333(4) 300 150 1 MHz ps ps ns Input Clock Jitter Tolerance(3) CLKIN_CYC_JITT_FX_LF CLKIN_CYC_JITT_FX_HF CLKIN_PER_JITT_FX Notes: 1. 2. 3. 4. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 26. CLKIN input jitter beyond these limits may cause the DCM to lose lock. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming clock frequency by two as it enters the DCM. Description Min Max Units DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 26 R Table 29: Switching Characteristics for the DFS -4 Speed Grade Symbol Output Frequency Ranges CLKOUT_FREQ_FX Output Clock Jitter(2,3) CLKOUT_PER_JITT_FX Period jitter at the CLKFX and CLKFX180 outputs All CLKIN <20 MHz CLKIN > 20 MHz Typ Max ps ps Frequency for the CLKFX and CLKFX180 outputs All 5 311 MHz Description Device Min Max Units See Note 4 [1% of CLKFX period + 100] [1% of CLKFX period + 200] Duty Cycle(5,6) CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs, including the BUFGMUX and clock tree duty-cycle distortion All [1% of CLKFX period + 400] ps Phase Alignment(6) CLKOUT_PHASE_FX CLKOUT_PHASE_FX180 Phase offset between the DFS CLKFX output and the DLL CLK0 output when both the DFS and DLL are used Phase offset between the DFS CLKFX180 output and the DLL CLK0 output when both the DFS and DLL are used All All 200 [1% of CLKFX period + 300] ps ps Lock Time LOCK_FX(2) The time from deassertion at the DCM's Reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX and CLKFX180 signals are valid. If using both the DLL and the DFS, use the longer locking time. 5 MHz < FCLKIN < 15 MHz FCLKIN > 15 MHz All 5 450 ms s Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 28. 2. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. 3. Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching). Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application. 4. Use the Spartan-3A Jitter Calculator (www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip) to estimate DFS output jitter. Use the Clocking Wizard to determine jitter for a specific design. 5. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle. 6. Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI. Example: The data sheet specifies a maximum jitter of "[1% of CLKFX period + 300]". Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 300 ps] = 400 ps. Phase Shifter Table 30: Recommended Operating Conditions for the PS in Variable Phase Mode -4 Speed Grade Symbol Operating Frequency Ranges PSCLK_FREQ (FPSCLK) Frequency for the PSCLK input 1 167 MHz Description Min Max Units Input Pulse Requirements PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period 40% 60% - DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 27 R Table 31: Switching Characteristics for the PS in Variable Phase Mode Symbol Phase Shifting Range MAX_STEPS(2) Maximum allowed number of DCM_DELAY_STEP steps for a given CLKIN clock period, where T = CLKIN clock period in ns. If using CLKIN_DIVIDE_BY_2 = TRUE, double the clock effective clock period. Minimum guaranteed delay for variable phase shifting Maximum guaranteed delay for variable phase shifting CLKIN < 60 MHz CLKIN > 60 MHz [INTEGER(10 * (TCLKIN - 3 ns))] [INTEGER(15 * (TCLKIN - 3 ns))] steps steps Description Units FINE_SHIFT_RANGE_MIN FINE_SHIFT_RANGE_MAX [MAX_STEPS * DCM_DELAY_STEP_MIN] [MAX_STEPS * DCM_DELAY_STEP_MAX] ns ns Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 30. 2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, i.e., the PHASE_SHIFT attribute is set to 0. 3. The DCM_DELAY_STEP values are provided at the bottom of Table 27. Miscellaneous DCM Timing Table 32: Miscellaneous DCM Timing Symbol DCM_RST_PW_MIN(1) DCM_RST_PW_MAX(2) Description Minimum duration of a RST pulse width Maximum duration of a RST pulse width Min 3 N/A N/A DCM_CONFIG_LAG_TIME(3) Maximum duration from VCCINT applied to FPGA configuration successfully completed (DONE pin goes High) and clocks applied to DCM DLL N/A N/A Max N/A N/A N/A N/A Units CLKIN cycles seconds seconds minutes minutes Notes: 1. 2. 3. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM DFS outputs (CLKFX, CLKFX180) are unaffected. This specification is equivalent to the Virtex-4 DCM_RESET specification. This specification does not apply for Spartan-3E FPGAs. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3E FPGAs. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 28 R Configuration and JTAG Timing Table 33: Power-On Timing and the Beginning of Configuration -4 Speed Grade Symbol TPOR(2) Description The time from the application of VCCINT, VCCAUX, and VCCO Bank 2 supply voltage ramps (whichever occurs last) to the rising transition of the INIT_B pin Device XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E TPROG TPL(2) The width of the low-going pulse on the PROG_B pin The time from the rising edge of the PROG_B pin to the rising transition on the INIT_B pin All XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E TINIT TICCK(3) Minimum Low pulse width on INIT_B output The time from the rising edge of the INIT_B pin to the generation of the configuration clock signal at the CCLK output pin All All Min 0.5 250 0.5 Max 5 5 5 5 7 0.5 0.5 1 2 2 4.0 Units ms ms ms ms ms s ms ms ms ms ms ns s Notes: 1. 2. 3. The numbers in this table are based on the operating conditions set forth in Table 6. This means power must be applied to all VCCINT, VCCO, and VCCAUX lines. Power-on reset and the clearing of configuration memory occurs during this period. This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 29 R Configuration Clock (CCLK) Characteristics Table 34: Master Mode CCLK Output Period by ConfigRate Option Setting Symbol TCCLK1 TCCLK3 TCCLK6 TCCLK12 TCCLK25 TCCLK50 Notes: 1. Set the ConfigRate option value when generating a configuration bitstream. See Bitstream Generator (BitGen) Options in DS312, Module 2. Description CCLK clock period by ConfigRate setting ConfigRate Setting 1 (power-on value and default value) 3 6 12 25 50 Temperature Range I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade Minimum 485 242 121 60.6 30.3 15.1 Maximum 1,250 625 313 157 78.2 39.1 Units ns ns ns ns ns ns Table 35: Master Mode CCLK Output Frequency by ConfigRate Option Setting Symbol FCCLK1 FCCLK3 FCCLK6 FCCLK12 FCCLK25 FCCLK50 Description Equivalent CCLK clock frequency by ConfigRate setting ConfigRate Setting 1 (power-on value and default value) 3 6 12 25 50 Temperature Range I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade Minimum 0.8 1.6 3.2 6.4 12.8 25.6 Maximum 2.1 4.2 8.3 16.5 33.0 66.0 Units MHz MHz MHz MHz MHz MHz Table 36: Master Mode CCLK Output Minimum Low and High Time Symbol TMCCL, TMCCH Description Master mode CCLK minimum Low and High time I-Grade Q-Grade ConfigRate Setting 1 235 3 117 6 58 12 29.3 25 14.5 50 7.3 Units ns Table 37: Slave Mode CCLK Input Low and High Time Symbol TSCCL, TSCCH CCLK Low and High time Description Min 5 Max Units ns DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 30 R Master Serial and Slave Serial Mode Timing Table 38: Timing for the Master Serial and Slave Serial Configuration Modes Slave/ Master -4 Speed Grade Min Max Units Symbol Clock-to-Output Times TCCO Description The time from the falling transition on the CCLK pin to data appearing at the DOUT pin Both 1.5 10.0 ns Setup Times TDCC The time from the setup of data at the DIN pin to the active edge of the CCLK pin Both 11.0 ns Hold Times TCCD The time from the active edge of the CCLK pin to the point when data is last held at the DIN pin Both 0 ns Clock Timing TCCH High pulse width at the CCLK input pin Master Slave TCCL Low pulse width at the CCLK input pin Master Slave FCCSER Frequency of the clock signal at the CCLK input pin No bitstream compression With bitstream compression Slave 0 0 See Table 36 See Table 37 See Table 36 See Table 37 66(2) 20 MHz MHz Notes: 1. 2. The numbers in this table are based on the operating conditions set forth in Table 6. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 31 R Slave Parallel Mode Timing Table 39: Timing for the Slave Parallel Configuration Mode -4 Speed Grade Symbol Clock-to-Output Times TSMCKBY Setup Times TSMDCC TSMCSCC TSMCCW(2) Hold Times TSMCCD TSMCCCS TSMWCC Clock Timing TCCH TCCL FCCPAR The High pulse width at the CCLK input pin The Low pulse width at the CCLK input pin Frequency of the clock signal at the CCLK input pin No bitstream compression Not using the BUSY pin(2) Using the BUSY pin 5 5 0 0 0 50 66 20 ns ns MHz MHz MHz The time from the active edge of the CCLK pin to the point when data is last held at the D0-D7 pins The time from the active edge of the CCLK pin to the point when a logic level is last held at the CSO_B pin The time from the active edge of the CCLK pin to the point when a logic level is last held at the RDWR_B pin 1.0 0 0 ns ns ns The time from the setup of data at the D0-D7 pins to the active edge the CCLK pin Setup time on the CSI_B pin before the active edge of the CCLK pin Setup time on the RDWR_B pin before active edge of the CCLK pin 11.0 10.0 23.0 ns ns ns The time from the rising transition on the CCLK pin to a signal transition at the BUSY pin 12.0 ns Description Min Max Units With bitstream compression Notes: 1. 2. 3. The numbers in this table are based on the operating conditions set forth in Table 6. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification. Some Xilinx documents refer to Parallel modes as "SelectMAP" modes. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 32 R Serial Peripheral Interface Configuration Timing Table 40: Timing for SPI Configuration Mode Symbol TCCLK1 TCCLKn TMINIT TINITM TCCO TDCC TCCD Initial CCLK clock period CCLK clock period after FPGA loads ConfigRate setting Setup time on VS[2:0] and M[2:0] mode pins before the rising edge of INIT_B Hold time on VS[2:0] and M[2:0]mode pins after the rising edge of INIT_B MOSI output valid after CCLK edge Setup time on DIN data input before CCLK edge Hold time on DIN data input after CCLK edge 50 0 Description Minimum Maximum (see Table 34) (see Table 34) See Table 38 See Table 38 See Table 38 ns ns Units Table 41: Configuration Timing Requirements for Attached SPI Serial Flash Symbol TCCS TDSU TDH TV fC or fR Description SPI serial Flash PROM chip-select time SPI serial Flash PROM data input setup time SPI serial Flash PROM data input hold time Requirement Units ns ns ns T CCS T MCCL1 - T CCO T DSU T MCCL1 - T CCO T DH T MCCH1 T V T MCCLn - T DCC 1 f C -----------------------------T CCLKn ( min ) SPI serial Flash PROM data clock-to-output time ns Maximum SPI serial Flash PROM clock frequency (also depends on specific read command used) MHz Notes: 1. 2. These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source. Subtract additional printed circuit board routing delay as required by the application. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 33 R Byte Peripheral Interface Configuration Timing Table 42: Timing for BPI Configuration Mode Symbol TCCLK1 TCCLKn TMINIT TINITM TINITADDR Initial CCLK clock period CCLK clock period after FPGA loads ConfigRate setting Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising edge of INIT_B Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising edge of INIT_B Minimum period of initial A[23:0] address cycle; LDC[2:0] and HDC are asserted and valid BPI-UP: (M[2:0]=<0:1:0>) BPI-DN: (M[2:0]=<0:1:1>) Description Minimum Maximum Units (see Table 34) (see Table 34) 50 0 5 2 5 2 See Table 38 See Table 38 See Table 38 ns ns TCCLK1 cycles TCCO TDCC TCCD Address A[23:0] outputs valid after CCLK falling edge Setup time on D[7:0] data inputs before CCLK rising edge Hold time on D[7:0] data inputs after CCLK rising edge Table 43: Configuration Timing Requirements for Attached Parallel NOR Flash Symbol TCE (tELQV) TOE (tGLQV) TACC (tAVQV) TBYTE (tFLQV, tFHQV) Notes: 1. 2. 3. These requirements are for successful FPGA configuration in BPI mode, where the FPGA provides the CCLK frequency. The post configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source. Subtract additional printed circuit board routing delay as required by the application. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA's LDC2 pin. The resistor value also depends on whether the FPGA's HSWAP pin is High or Low. Description Parallel NOR Flash PROM chip-select time Parallel NOR Flash PROM output-enable time Parallel NOR Flash PROM read access time For x8/x16 PROMs only: BYTE# to output valid time(3) Requirement Units ns T CE T INITADDR T OE T INITADDR T ACC 0.5T CCLKn ( min ) - T CCO - T DCC - PCB T BYTE T INITADDR ns ns ns DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 34 R IEEE 1149.1/1553 JTAG Test Access Port Timing Table 44: Timing for the JTAG Test Access Port -4 Speed Grade Symbol Clock-to-Output Times TTCKTDO Setup Times TTDITCK TTMSTCK Hold Times TTCKTDI TTCKTMS The time from the rising transition at the TCK pin to the point when data is last held at the TDI pin The time from the rising transition at the TCK pin to the point when a logic level is last held at the TMS pin 0 0 ns ns The time from the setup of data at the TDI pin to the rising transition at the TCK pin The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin 7.0 7.0 ns ns The time from the falling transition on the TCK pin to data appearing at the TDO pin 1.0 11.0 ns Description Min Max Units Clock Timing TCCH TCCL FTCK Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6. The High pulse width at the TCK pin The Low pulse width at the TCK pin Frequency of the TCK signal 5 5 - 25 ns ns MHz DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 35 R Revision History The following table shows the revision history for this document. Date 08/31/07 01/20/09 Version 1.0 1.1 Initial Xilinx release. * * * * * * * * * * Revision Updated "Key Feature Differences from Commercial XC Devices." Updated TACC requirement in Table 43. Updated description of TDCC and TCCD in Table 42. Removed Table 45: MultiBoot Trigger Timing. Added package sizes to Table 2, page 4. Removed Genealogy Viewer Link from "Package Marking," page 5. Updated data and notes for Table 6, page 8. Updated test conditions for RPU and maximum value for CIN in Table 7, page 8. Updated notes for Table 8, page 9. Updated Max VCCO for LVTTL and LVCMOS33, removed PCIX data, updated VIL Max for LVCMOS18, LVCMOS15, and LVCMOS12, updated VIH Min for LVCMOS12, and added note 6 in Table 9, page 11. Removed PCIX data, revised note 2, and added note 4 in Table 10, page 12. Updated figure description of Figure 5, page 14. Added note 4 to Table 13, page 14. Removed PC166_3 and PCIX adjustment values from Table 17, page 17. Deleted Table 18 (duplicate of Table 17, page 17). Subsequent tables renumbered. Removed PCIX data Table 18, page 18. Removed PCIX data and removed VREF values for DIFF_HSTL_I_18, DIFF_HSTL_III_18, DIFF_SSTL18_I, and DIFF_SSTL2_I from Table 19, page 19. Updated TDICK minimum setup time in Table 20, page 20. Updated notes, references to notes, and revised the maximum clock-to-output times for TMSCKP_P Table 24, page 22. Added "Spread Spectrum," page 24. Updated note 3 in Table 26, page 25. Added note 4 Table 28, page 26. Updated notes, references to notes, and CLKOUT_PER_JITT_FX data in Table 29, page 27. Updated MAX_STEPS data in Table 31, page 28. Updated ConfigRate Setting for TCCLK1 to indicate 1 is the default value in Table 34, page 30. Updated ConfigRate Setting for FCCLK1 to indicate 1 is the default value in Table 35, page 30. 09/09/09 2.0 * * * * * * * * * * * * * * * * Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 36 R Automotive Applications Disclaimer XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 37 |
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